A typical solid-state imaging sensor device is composed of a charge-integrating photosites arranged in rows and columns. Each photosite responds to incident radiation by providing an electrical signal corresponding to one pixel of frame information. In the interline transfer type, charge is transferred out at once into a parallel structure of vertical shift registers. First, a charge pattern is accumulated at integration sites during image acquisition period, then the charge pattern is transferred into storage columns, also known as vertical shift registers. The transferred charges are then shifted one line at a time, into a horizontal readout register from which a line-by-line 2D video output signal is taken. This is known in the prior art and commonly allows taking pictures at a frame rate of about 30 frame per second.
Also known in the prior art is the use of such CCD cameras in acquiring profiles of objects for surface geometry inspection and measurements of relatively small objects. This is done by illuminating the surface of the object by an incident high energy light plan usually coming from a laser, and capturing the reflected light on the CCD image sensor array. Then, the acquired profile of the object can be isolated for shape or surface geometry inspection of the object. A limitation of the known technique comes from the fact that when many surface portions have to be inspected in a short period of time (e.g., on a assembly-line) the standard frame rate of the CCDs is no longer sufficient, because the known method allows inspecting at most one profile per frame period per CCD camera. Various improvements to the known technique are disclosed in U.S. Pat. No. 4,162,126 to Nakayama et al., U.S. Pat. No. 5,083,867 to David Burk and U.S. Pat. No. 5,177,556 to Marc Rioux.
There are also other prior U.S. patents that allow improvements concerning the frame rate being read from a CCD sensor. This is done by formatting the area sensor into blocks of photosites so that fewer sectors have to be read (e.g. U.S. Pat. No. 4,322,752 to James Bixby) or by adding adjacent pixel charges to improve at the same time the acquisition frame rate and the dynamic range of the image (e.g. U.S. Pat. No. 5,420,629 to Takashi Watanabe). None of these prior patents allow a standard interline transfer CCD to be used having an improvement of a factor greater than 4 over the standard read rate and, when there is improvement, this is done at the expense of detail or quality of the captured image.